Efficient AI, closer to the edge.
I design hardware-aware deep learning systems for resource-constrained devices, with a focus on FPGA acceleration, fixed-point quantization, and efficient inference. My work is about making intelligent systems not only accurate, but practical to deploy.
My research sits between deep learning and the hardware it runs on. I focus on FPGA-based inference acceleration, fixed-point quantization, and efficient data movement for edge devices with limited memory, bandwidth, and power.
I am especially interested in the gap between model design and deployment: the point where a neural network stops being only an algorithm and becomes a working system with timing behavior, memory constraints, and energy costs. Much of my current work explores these trade-offs through tiled CNN accelerators on FPGA platforms.
Alongside research, I care about teaching, technical writing, and practical engineering education. I want my work to contribute not only to academic research, but also to helping learners understand embedded systems, digital hardware, and efficient AI from first principles.
- now
- TileCNN — schedule-driven FPGA acceleration for heterogeneous convolutional layers.
- 2025
- Published a fixed-point workflow bridging neural-network quantization and FPGA deployment at DDECS.
- 2024
- Published TinyEmergencyNet, an ultra-lightweight model for aerial scene classification.
- open
- Research collaborations and conversations in embedded AI and FPGA acceleration.