Bridging Quantization and Deployment: A Fixed-Point Workflow for FPGA Accelerators
Abstract
We present a fixed-point quantization-to-deployment workflow that automates the precision-selection and hardware generation steps for deep learning accelerators on FPGAs, closing the gap between post-training quantization research and practical synthesis-ready RTL.
Citation
@inproceedings{mogaka2025ddecs,
author = {Mogaka, Obed M. and Forsberg, Håkan and Daneshtalab, Masoud},
title = {Bridging Quantization and Deployment: A Fixed-Point Workflow for {FPGA} Accelerators},
booktitle = {Proceedings of the 28th International Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS)},
year = {2025},
pages = {123--126},
doi = {10.1109/DDECS63720.2025.11006791},
keywords = {FPGA, quantization, deep learning, hardware accelerator, fixed-point}
}