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Research project

FixQuant

Fixed-point quantization for CNNs that must run bit-exactly on FPGA accelerators, from quantization-aware training to a verified deployment package.

FixQuant pipeline. An FP32 model goes through quantization-aware training, is validated by an integer digital twin that is bit-exact with the FPGA, is released as a versioned model, and is exported as a deployment package.

Quantization research often stops at model accuracy, while hardware implementation starts from a separate set of fixed-point and interface decisions. FixQuant closes that gap. It trains 8-bit fixed-point CNNs, checks their integer arithmetic in software before any hardware is involved, and ships them as versioned, checksum-verified packages that an FPGA accelerator can compile directly.

FixQuant is the model-preparation component of TileCNN, my reusable model-to-FPGA framework.

What it does

  • Trains in fixed point. Quantization-aware training with Trained Quantization Thresholds (TQT) learns power-of-two scales for 8-bit weights and activations. It uses MSE calibration and optional cross-layer equalization.
  • Validates before hardware. An integer digital twin reproduces the accelerator’s convolution, requantization, pooling, and residual arithmetic bit for bit. Deployed accuracy is therefore known before a bitstream is built.
  • Ships reproducible releases. Every model is an immutable, versioned release with recorded accuracy, quality gates, and SHA-256-pinned artifacts. Nothing is fetched implicitly, and nothing is transcribed by hand.

The exported package contains the network graph, integer weights and biases, validation inputs, and integer reference outputs. A manifest records the release identity, preprocessing, and a checksum for every file.

Model zoo

Top-1 accuracy (%) on the full ImageNet-1k validation set (50,000 images). FP32 is the pretrained floating-point model, QAT is the trained fixed-point model, and Integer twin is the bit-exact integer model that the FPGA executes.

ModelFP32QATInteger twinΔ
ResNet-1869.7570.0569.74−0.01
ResNet-5080.3479.9579.58−0.76
VGG-1671.5871.2471.00−0.58
MobileNetV272.0171.5770.95−1.06

Δ is the end-to-end change from FP32 to the integer twin. MobileNetV2 uses cross-layer equalization.

Publication

The workflow was published at the 28th IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS 2025).

Published work

  1. Obed M. Mogaka, Håkan Forsberg, Masoud Daneshtalab Bridging Quantization and Deployment: A Fixed-Point Workflow for FPGA Accelerators . Proceedings of the 28th International Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS) , 2025 .