Research project
Fixed-Point Quantization-to-FPGA Workflow
A deployment workflow that connects neural-network quantization decisions to practical FPGA accelerator implementation.
Quantization research often stops at model accuracy, while hardware implementation begins with a separate set of fixed-point and interface decisions. This project studies the missing connection between those stages.
Objective
The goal is to make fixed-point deployment more systematic: select a suitable numerical representation, preserve the intended model behavior, and carry the resulting parameters into an FPGA implementation without treating quantization and hardware generation as unrelated tasks.
Contribution
The workflow organizes the path from a trained neural network to accelerator-ready fixed-point data. It focuses on the engineering decisions that determine whether a quantized model can be reproduced reliably in hardware, including numerical formats, conversion, validation, and deployment.
The work was published at the 28th IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS 2025).
Related publication
Published work
- Bridging Quantization and Deployment: A Fixed-Point Workflow for FPGA Accelerators . Proceedings of the 28th International Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS) , 2025 .