TileCNN

TileCNN is my current FPGA-accelerator research platform. It explores how a single hardware design can support convolutional layers with different spatial dimensions, channel counts, kernel sizes, and strides without rebuilding the accelerator for every layer.

Research problem

Neural-network accelerators are often optimized around one dataflow or a narrow set of layer shapes. That specialization can deliver excellent peak performance, but it also makes the design expensive to retarget as networks change. In practice, useful deployment requires both efficiency and enough flexibility to handle heterogeneous layers.

Approach

TileCNN separates the execution policy from the compute datapath. Host software describes tiled work through compact schedules, while the FPGA kernel focuses on predictable data movement and computation. This makes scheduling, memory reuse, and layer mapping software-controlled research questions instead of hard-wired assumptions.

The work brings together:

• tiled convolution and streaming dataflow;
• descriptor-driven hardware/software co-design;
• on-chip memory and external-memory traffic management;
• fixed-point inference and bit-exact verification;
• layer-wise performance characterization on FPGA hardware.

Status

This is active PhD research. The implementation, experiments, and publication material are being refined, so this page intentionally presents the public research direction rather than unpublished repository details.